Binary multiplier



June Z1, 1960 B. o. MARSHALL, JR., ETAI- 2,941,729

BINARY MULTIPLIER Filed Aug. 25, 1958 8 Sheets-Sheet 1 -mkl ill?

IN VENTORS 3 )4604/ 0. M/MS//l June 21, 1960 B. o. MARSHALL, JR., ETAL 2,941,720

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INVENTORS June 21, 1960 B. o. MARSHALL, JR, ErAL 2,941,720

BINARY MULTIPLIER 8 Sheets-Sheet. 4

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BINARY MULTIPLIER 8 Sheets-Sheet, 5

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BINARY MULTIPLIER 8 Sheets-Sheet 8 Filed Aug. 25, 21.958d

United States yljatent O y BINARY MULTIPLIER Byron O. Marshall, Jr., Park Ridge, lll., `(120 S. La Salle St.,'Chicago 3, IIL); and John D.`Dillon, 1001 Riverside Drlve, Indialantic, Fla.`

Filed Aug. 25, 1958, Ser. No. '157,160 6 Claims. (Cl. 23S-164) (Granted under Title 35, U.S. Code (1952), sec. 266) The invention described hereinimay be manufactured and used by or for the Government for governmental purposes without payment to us of any royalty thereon.

This application is a continuation-impart of our application, Serial No. 301,007, filed July 25, 1952, now abandoned.

The invention described herein relates to binary computing apparatus and particularly to binary multiplication in Vwhich the binary numbers involved have their digits represented by distinguishable electrical signals. 'Ilhe object of the invention is to provide means for multiplying two multi-digit binary numbers in which the electrical signals representing the digits of the numbers may occur ineither serial or parallel form. The multipliers described require, where the number of digits isgreater than three, the use of binary column adders for finding the sum and carries for a column of more than three digits. An additional object ofthe invention, therefore, is to provide a column adder capable of use with any number `ofiiigits greater than threeand employing as components simple two and three digit column adders already known in the art.

A more detailed description of the invention will be given with reference -to the accompanying drawings, in which Fig. l is a schematic diagram of a multiplier inaccordance with the invention for binary numbers in serial form;

Fig. 2 gives waveforms occurring in Fig. l; Fig. 3 represents schematically a possible construction of the input and control portion of Fig. 1;

Fig. 4 illustrates the construction of a serial column adder for accommodating any predetermined number of column digits, in this case 15;

Figs. 5` and 6 illustrate a multiplier for binary numbers in parallel form;

' Figs.I 6a-6d show column adders employed in Fig. 6;

d Fig. l7 illustrates the construction of a parallel column adder `for accommodating lany predetermined number of column digits, in this case l2; Fig. 8 shows a suitable basic 2-variable binary adder for use in the described column adders; and

` Fig. 9 shows a` suitable basic 3-variable binary adder for use in the described column adders.

vThe multiplying apparatus described operates with binary numbers the digits l and 0 of which are represented by positive and `negative electrical pulses, respectively. If the numbers are in serial form the pulses occur in succession separated by a` fixed repetition interval T, the least significant digit occurring iirst. If the numbers are in parallel form the pulses representing the digits occur simultaneously in separate circuits.

A simple problem in binary multiplication is shown below.

1101 (multiplicand) 1011 (multiplier) 11101 (partial product) 12101 (partial product) 0000 (partial product) 1101 (partial product) 10001111 (product) CCu appropriately delaying the multiplicand, and the partial products are summed by a single column adder which adds the-partial product digit columns in succession starting with the least signicant. The maximum number of simultaneously occurring digits that the column adder must be capable of accepting is, as seen from .the above problem, equal to the number of multiplier digits. The digits of the final product appear at the output of the column adder in succession. In the parallel multiplier, a separate circuit is provided for each digit of the final product. Each circuit, save that representing the least significant digit, contains a column adder, the column adder operating simultaneously 'to provide the column sums, which constitute the digits of the product, and appropriate carries to higher order columns. The serial multiplying apparatus, shown in Fig. l, will be described first.

For simplicity the serial multiplying apparatus shown in Fig. l is restricted to multipliers and multiplicands of four digits, however, any number of digits may be accommodated by simply extending the procedures shown. To start with it will be assumed that multiplicand and multiplier, represented in -serial pulse form with a posi- -tive'pulse representing the binary digit 1 and a negative pulse representing the binary digit 0 and with a pulse repetition interval T, are stored in suitable storage devices `1 and 2.. These storage devices may be of any suitable known type. For example, they may be delay loops around which the series of pulses representing the binary number circulates continuously with the least significant digit appearingv at the output terminals 3 and 4 at definite predetermined times and followed in succession by the digits `of increasingly higher order. A negative pulse generator 5 is provided and operates continuously to produce a series of negative pulses, representing binary zeros, with the pulses separated by a constant interval T. There is also provided a sequence control apparatus or circuit 6 the function of which is to control and time the various operations of the multiplier process. When the multiplier is acomponent of a digital computer the clock pulses provided by the computer for maintaining synchronization throughout the system would normally also be applied, as over line 7, to elements 1, 2, 5 and 6 for synchronizing purposes.

The operation of Fig. l will be explained with reference to the waveforms of Fig. 2 in which the numbers refer to the lines in Fig. 1 in which the waves occur. At to a short start pulse is applied to sequence control circuit 6 over line 8. It will be assumed that the insertion of the multiplier and multiplicand into storage devices 2 and 1 was arranged so that the least signicant digit of the multiplicand occurs at terminal 3 at an interval 4T later than the occurrence of the least signicant digit of the multiplier at terminal 4. With this preairangement to is chosen as the time at which the least significant digit of the multiplier is at output terminal 4 of the multiplier storage device.

Upon application of the start pulse to circuit 6 over line 8 at lo the sequence control circuit acts to produce a steady voltage on line 9 extending from tu to slightly past t3, as shown in Fig. 2. This voltage actuates switch S1 which connects terminal 4 over line 10 to input terminal 11 of delay line 12 yfor this interval. The delay line contains at least three equal sections each made up of series inductance L and shunt capacitance C andproducing a delay T. The line may be terminated in its characteristic impedance Zo. Since the least significant digit of the multiplier appears at terminal 4 at to and the pulses representing the multiplier appear simultaneously at delay line points l11, 13, 1 4 and .15 with the. pulse. representingjthe least significant digity at point 15. For the problem givenabove, inY which the multiplier is 101'1, the polaritiesof'these points at. t3 will be as indicated in Fig. l.

"".The points 11,13, Meand 15 are connected through blockingcondensers to the control grids ofgas triodes 16,v 17,13 and1`9, The grids oithese'triodes are biased negatively relative'V to 'their cathqdes by' voltage source 2.0..f Voltage source 2i; supplies positive potentialto the anode'soilthe gastubes4 tliroughthe actuating coils of switches S2, .53, S4 and S5; TheA gastriodesl Iare initially noncon- Yductive and the negative blason their grids, suppliedby source '29,' is made sutliciently great that positive potentials'appl-iedrto the grids asthe result of pulsesrepresentingrthe multiplierv digits travelling along delay line 12. are not ableA to overcome the bias and fire the tubes. However, vat t3, at. which time pulses representing, the four binary digits, are atY points 1l, 13, 14 and 15 of the delay line, sequence control circuit 6 produces a positive pulse on line 22"wh`ich is applied simultaneously to the grids of tubes 16-19. This pulse acting alone is insuicient to overcome the bias from source 20 and firethe gas tubes, howcvenring will occur. when the pulse acts in combina, tion with' a positive pulseon thegrid' from the delay'li'ne.r Accordingly/,fertile aboveproblein, tubes 16,A 1SY and A9 will lire attg, since there are coincident positive pulses on.

their grids' at that time., Tube 1.7will not fire since the pulse appliedV to' its grid bythe delay line is negative. Firing of'tubes, le and 19 actuates switches Srandl Sg to their b contacts.

f As.. mentioned'above, the least significant digit ofthe multipl-icand' appears at output terminal 3` of storage device 1 at an interval' 4T later than the appearance at lo of. the'l'east signicant digit' ofA the multiplier at terminal 4i Therefore, the least significant digit ofthe multipl-icand occurs at terminal 3 at t4'. At. t4 sequence control circuit 6' produces a steady voltage on line 23 which persists until slightly after t7., Therefore, switch Sgl is'actuated for this period' andthe series of pulses representing. the multipriicand' flows through'contacts Seb to multiplicand termin'alfZ/i, least 'significant digit iirst., Prior to t4 and subsequent. to. t7, negative pulses from.v generator 5, which appear' continuously on line Z5, `are appliedto conductor 24 through. contact Sea. Also at t4 control circuit 6 produces avoltagc. .online 26 which actuates S, and connects output terr'n'nal` 27 of the multiplier to output` line 28. The duration of this voltage is madesufiicient toVL accommodate the final product,l in'this case to slightly beyond 4 i its negative pulse at t3 from terminal a but from terminal b via contactv Sgm and multiplicand terminal 24. In the case of terminal 29, the negative pulse occurring at t3 appeared at terminal 24 .also` at t3. For terminal 30, the negative pulse occurringjat t5, appeared at terminal 24 at r2 and was delayedvby A an intervalV T in delay circuit $3,v Similarly, for terminals 31 andi 32,'the negative pulses occurring at tg appeared at'terrninal 2'4L-atf t1. and-'rrespectively, and were subjected to delaysjo 2T and"31` by delay elements 1*"4'-and"l 35;

Terminal 29 is associated'withfswitchf S5 which is set in accordance. with: the least` signiiicari digit, the. multiplier.

A IvfY this digit is 0, S5` is not actuated and negative pulses from generator 5 continue to, be applied to terminal ""29.y thmughV contact 85a. Ofn the other hand, if the least sig; nifcant digit is. 1S5will have been. actuated at. t3 and. the" series. ofpulses representing the 1 digitsv of the multiplicand.

are applied -through contact S51, to terminal 29, least sigg;V

nilicant digit lirst, duringthe lgieriodtg-t, and constitutetli'e' least.signiiicantpartial.product.

v The terminali. 3.1i is associated with switch Sgwhichis, set. in. accordance with the nextv higher order multiplier digit. If` this digit-is. O, S5 is not. 'actuatedv andv negativel pulses continue to be applied' to terminaltl through ceutact. Srta... However, if this digitV is 1, Slwillhave been actuated at t3 and', the series of pulses representingI the'` digitsfof'theV multiplicandafter a delay off lTindeIaSi l circuit33 areapplied to terminal 3U through contact- Sth.

during. the interval :f5-t8. and constitute.V the next higher Orl-1 der. partial product, the` delay of 1T in. efect.multiplying;`

the multicplicand byf2v1 to formthe partialproduct..` Yflhe negativepulse from. generator, 5. that. occurred onllinezllf at.A t, just. prior to theA operation. otSgat 14,. appears af tenninaldil at t4.' p I In amanner similar to the above, the-partialprodilts due tothe third and fourth digitsof the multiplier, When these digits are l, appear at partial product terminalsl and 32, respectively, and are produced by delaying-the mult-iplicand by 2T and 3T to, in eiect,.multiply. it by 2? and 23. Accordingly, the digits of the multiplicand. apfA pear at terminal 31 at ttf-t9 and at terminal` 32 at 12,4410.' The, two negative pulses from generator 5 that. appeared at terminal 24 atv tzand t3 appear. at terminal 31 at ligand.

i generator S are restored on terminal 24 through contact columns appearV simultaneously at partial product terminals 29?, 3ft, 31 andV 32. with the. columns appearing in succession. at intervals of T, the least si'gnlicant column appearing iirst. The following analyzes the formation of theA partial products and thepartial product digit columns in detail:

Brion to. t3;- negativeV pulses from generator 5 are con-l tinu'ously applied to partial product terminals 29-32 through. thec-contactsof switchesV S2455. -lnthe manner explained, above,these switches. are set at t3? in accordance with themultipliendigits, the switchVA being actuated ifV the corresponding multplien digit is l; and, remaining unactuatecl. ii the corresponding digit is' 0. Eachl of the terminals: 21%32l that associated withV inactuated switches. receives. negativel pulses at z3 and subsequently from;v generator 5 through. contact a of. its associatedv if Sea. at 1B. Sincethelast digit of themultiplicandwas applied-to this terminal at tq there -is no breakinrthe pulses applied to those of, terminals 29- 32 whoseY associated switches (S2-S5) are actuated. It willl thereforebe. api` parent rom'the; above discussion that each ofterminals 29-32 will have negative pulses fromfgenerator 5 applied to'k it .except during the time that theV significant digitsqof the multiplicand arebeing applied. Fig. 2 shows, at the Correspondingly numbered places, the pulses occurring at` terminals 29-32 for the above given specific problem..y in which the multiplicand is :1 and the multiplier is 1011.

rEhe4 function of the column adder 36 is to sumv the columns of digits formed by the partial products. From theabove it is seen. that the pulsesrepresenting these columns ou. digits. appear on terminals29-32 fromz try-to im. The column; adder must produce the-column-.sum.ofl the column digits .plus any carries. to theiparticular column from lower order columns. The column sum digits con: stitute the digits ofv the iinal product. Allowing for one carry from the highest order column the highest order digit possible in the final product occurs at r11. Therefore, the switch S7 is actuatedz for the period t4 to slightly beyond tu, as enplained earlier.

Because ofthe carries. the inputsto. the column adder are in two categories: the .column digitor. external inputs, which in Fig. l are the terminals A2?-3t2,.and the carry or internal inputs which inll'ig.A 1;. are designated C1 and C3.

eThe number of external inputs always equals vthe number of partial products, or the number of digits in the multiplier, and is four for the 4-digit apparatus of Fig. l.' The number of carry or internal inputs depends upon the number of external inputs in a manner that will be ex` Plained later. Two carry inputs, designated vC1 and C2,

, :are required in F-ig. l. i

' The column adder 36 is a combination of basic 2- variable and 3variable binary adders, specific examples of which will be given later. The basic 2variable adder 37 has two input terminals a and b, a sum output terminal s and a carry output terminal c. The response of the 2- variable -adder to and input pulses is as follows:

one tive Inputs a and b a c botn++ one one both l The basic 3-vau'ab1e binary 'adders 38, 39 and 40 are all alike and have three inputs a, b and d and sum and carry outputs designated s and c. The response of the 3-Variable added to and input pulses is as follows:

Inputs a, b, and d l s t c 11+ two one ,-I- oe, two a t .each basic adder to one of the inputs of the next adder in the cascade, the sum output of the last adderinthe cascade being the column sum and constituting the-digit of corresponding order in the final product. In Fig. 1, the column sum appears at terminal 27. The three carry outputs (c) produced by the cascade of basic adders are then applied as inputs to 3variable adder 40, the sum output (s) of which, appearing at terminal C', isthe carry to the next higher order column and the carry output (c) of which, appearing at'terminal C", is the .carry to the second higher order column. The column adder provides means, in the form of delay elements 41 and 42, to store these carries for periods of 1T and 2T, respectively, until the corresponding higher order column digits appear at terminals 29-32. The response of column adder 36 to pulses at the six input terminals 2932, C1 and C2 is as follows:

Inputs 29, 30, 31, 32, C1, C;

The wave forms occurring at input terminals 29-2, C1 and C2 of the column adder, and the waveform of the final product appearing at outPut terminal 27, are shown" 'I at the correspondingly numbered places in Fig, 2, The

leastsigniiicantrdigit of the final product occurs' at t4' and the latest possible occurrence of the most significant digit of the product, for the apparatus of Fig. l, is tu. The

voltage on line 2-6, therefore, is terminated by the se? quencecontr'ol circuit *6 at slightly after tu and S7' is' released disconnecting the multiplier from the output line 28. At tu the sequence control 6 produces a short pulse on line 43 which momentarily actuates switch S8. The resulting momentary removal of anode voltage from gas triodes 16-18 extinguishes those that were conductive and restores the associated switches to their initial deen ergized state. 'Ihis completes the cycle of operation of the multiplier.

The elements 5, 1, 2 and 6 of Fig. l would normally be electronic in nature utilizing any of the means known in the art for accomplishing their functions as described above.` However, a simple electromechanical embodiment of these elements is shown in Fig. 3. in this embodiment, in which the reference numerals correspond to those used in Fig. l, each of the elements 5, 1, 2 and 6 is a rotary device mounted on a common shaft 7 which, in effect, performs the synchronizing function of line 7 in Fig. 1. 'Ihe negative pulses on line 25 are generated by a contact wheel 44. The multiplicand. and multiplier storage devices 1 and 2 are magnetic drums 45 and 46 on which the digits of the4 multiplicand and multiplier have been magnetically recorded earlier at the locations. indicated bytheir times of entry into the multiplier cycle, as indicated in Fig. 2. The function of theisequence control circuit I6 is performedin this embodiment by a contact wheel 47 on which there are contacts having the proper locations and angular extents to produce the control voltages required by the multiplier apparatus. Upon application of a short start pulse to circuit 8, latch 48 for latched wheel 49 is momentarily withdrawn allowing shaft 7 to make one complete revolution at a constant speed under the inlluence of torque motor S0. The multiplier cycle of operation is completed in one complete rotation of shaft 7'. H

The various switches of the multiplier in Fig. 1 arev shown as electromechanicalA for simplicity. These switches may be replaced by electronic types where greater speed of operation is required.

Also, for simplicity, the multiplier of Fig. l was restricted to a capacity of four digits for the multiplier and multiplicand. However, the procedures and apparatus described may be extended to accommodate binary numbers of any number of digits. Also the serial column adder 36 of Fig. l may be expanded to accommodate any number of column digits. The procedure is as follows:

n=number of input variables exclusive of carries, c=number of carries, and N (n+c) :input variables including carries.

. (l) Approximate number of carries by f determining maximum value of c forwhich 2cn. ,l

(2) Add approximate value of c to n to find approximate value of N.

(3) Determine maximum value of c for which ZUN. If c has different value from that determined in (l) recompute (n+c) and solve for maximum value of c again. Repeat `until c does not change. This is true value of c which added to n gives `true value of N. p

(4) Form a first adder section consisting, when N is even, of one basic 2-variable adder and basic 3-variable adders, or, when N is odd, consistingof (N- l) 3-variable adders, the adders in the section beingcascaded by connecting the sum output of each 'basic adder `to one of the inputs of the next basic adder in the cascade.

The sum outputof the last basic adder in the cascade con stitutes the column sum. (5) Letting c' equal the number of carry outputs of 2 sa ma c anda C! (ad) 3-varia'ble adders, and when c' isodd, consisting of 3-variable adders. Cascade second section withV first section by connecting .carry outputs of first' section to re'- maining inputs of .second sect-ion.` The sum output of the second section constitutes the carry to the next higher order column. vThis output is delayed by ian interval equal to one digit separation interval and applied to an input of the rst section.

(6) Repeat (5)., letting c' equal the number of carry outputs of lthe preceding vsection,'until a section containing a single basic 2-variable or 3-variable adder is formed. The sum outputs of ythe succeeding sections, with appropiiatetdelays, are applied to inputs of the first section. The rcarry outputs of each succeeding section, save the last, lare applied to the inputs ofthe next succeeding section. The carry output of the last section, appropriately delayed is .applied to the input of the first section. f .As a specific example, the design of a serial column adder for `n=l5 in accordance with the foregoing procedure is as follows, the resulting :adder .being shown'y in Figli: l V 1) Maximum yvalue of c for which ZelS is 3.

(2) n-|-c=l8.Y v

. I(fil) .Maximum value of cl for which 2Cl8 is, '4- n-l-,c.=-1.9.A MaxirnurrrvalueY of c for which 20%19 Iisf4: Therefore 4 is true value of c, and truer value ci N-zn-l-cw. ...(4.1) Since 1'9 is odd, 'first section consistsv of,

I N -e l v i ).29 svariable adders'. ,(5) Since. c-=9.is odd, second .section consists of c -lf i 2 Marianeadders. x l (6) (a) Since c'=4 is even, third section consists of one Q-Variahleadder and 4 c l (-*Qal .9i-variableadders. (b) Since c=2 is even, fourth section consists of one Z-variable adderand '3f-variable adders. Therefore fourth is last section.

Parallel multiplication, in which the electrical potential representing the multiplier and multiplicand occur simultaneously in separate circuits rather than in succession 'in the same circuit as serial multiplication, lis performed by the apparatus shown in Figs. and 6. fFor convenience the capacity of the multipler shown is limited to binary numbers of ve digits, however, the structure and proceduresshown can be extended to accommodates binary umbersof any number of digits.

Referring to Fig. 5, the digits of the multiplicand appear simultaneously on conductors S0-54 in the form of a voltage of positive polarity `for the digit 1 and of negative polarity for the digit 0. These voltages may be supplied through the switches shown associated with conductors 50-5-4, the down position of a switch. representing binary 1 andthe lup position binary '0. The voltage representing the least significant digit of themultiplicand appears onconductor and that representing the most significant digit .appears on conductor 54. .Y I Switches v55459 `are set in .accordance withV the digits of the multiplier, switch corresponding to the least significant digit and switch 59 corresponding to the most signicant digit. Each switch is in its upper or lower .position depending upon whether the corresponding multiplier digits is 0 or 1. Each switch has as many banks of S.P.D.T. contacts as there are digits in the rnutiplicand. The function of switches 55-59 is to connect the appropriate partial productdigit conductors to conductors` 50-54 for the 1 .digits in the multiplier and torconnect the appropriate partial product digit `conductors to negative potential for the 0 digits in the multiplier. The partial product digit conductors are numbered in accordance with theV partial product digit coluxnnhto which Vthey pertain.4 For example, the partial product due to the least signifi-- cant multipler digit appears on ,partial ,piiidiic't digit conductors 0, 1', 2", 3 and 4" which, disregarding the primes, are numbered in accordance with the columns in which the digits of this partial product appear. Similarly, the partial vproduct due to the second multiplier digit (switch 56) appears on conductors 1, 2', 3", 4"'--ancl 5w; ythe partial product due to the third multiplier digit appears on conductors 2, 3', 4", 5" and 6"; etc.

.As seen in Fig. 6, a parallel column adder is provided for each partial product-v digit column, exceptV the leastsignificant which contains only a single digit... .Thepart-ialproduct digit columns in Fig. 6 are designated'Co'l. "0 through CQLS, Col 0 being the least significant. These adders are termed parallel column adders since they all producey theircolumn sums and carries to higherorder columns at the Asame instant, rather than column by column as Vfor the serial column adder. l 'lf-"ne number of inputsrequired for each column 'adder isequal to the maximum number of partial product digitsin the column plus the carries from lower order columns. For example,` the adder for Col. 4 of iFig. 6 must accommodate live partial product digits and `two carries so that a 'Z-variable column adder is required. The other column adders require various .lesser numbers of inputs as indicated in Fig. 6. The additional Z-Variable adder 60 is required because of thepossibility of a carry from Col. 8. Lines Sl-SB are the .sum outputs of the respective vcolumn adders. The digits of the final product appear simultaneously on lines S0-S9, the least significant appearing on line S0. The column adders of more than3 variables are made up of basic 2-variable and 3-variable adders and are shown in Figs. 6a, 6b, 6c and 6d. I

Although, for simplicity, the multiplying apparatus o f Figs. 5-6 is restricted to 5-digit binary numbers, the .apparatus may be expanded to accommodate .numbers of any desired number of digits. The expansion would merely involve duplication of the components'shown in Figs 5 and 6 for the higher order digits and the provision of parallel column adders of the required number of-i-nputs. As in the case of serial column adders, parallel column adders of any numberof input variables may be constructed from basic 'Z-vai'iable' and 3 -vaii'ble 'adders The design is'similar to the design of serial column adders 'except thatV the number of carry inputs does not`necessrily: equal the number of-carry outputs as inthe c asejof` 'ther' serial column ad'der.'."A YVsomewhat;'simljgilified design. prpcedure therefore results. AThe -simpliiiedjprccedureg for designing'anN-'vaiiiable parallel column adder .is as:

(l) Form a first adder sectionV consisting, whenN'is even, of one basic 2-variable adder .and

basic -'variable adders, or, `when N is odd, consisting vof estarse (I3-'fili 3variable adders, and, when c is odd, consisting S-Variable adders. Cascade lsecond section with rst section by connecting carry outputs of rst section to remaining inputs of second section. The sum output of the second section constitutes the carry to the next higher order column. d

(3) Repeat (2), letting c equal the number of carry outputs of the precedingsection, until a section containing a single basic 2-variable or 3-variable adder is formed. The carry outputs of each succeeding section, save the last, are applied to the inputsof thenext succeeding section. p The sum outputs of the succeeding sections plus the carry output of the last section constitute the. carries to higher order columns. i

As an example, the design of a l-2digit parallel column adder is as follows: ,y d d .A

(1) vSince N=12 is even, the rst section consistsfof one 2variable adder and f (rlb S-variableadders. l' l l (2) Since c=6 for first section is, even, the second section consists of one 2`variable and Since c"=3 for second section is odd,

3-variab1e adder.

Suitable basic 2va1iable and 3-variable adders for use in Figs. 1, 4, 6, 6a-d and 7 are shown in fFigs. 8 and 9. The Z-Variable adder of Fig. 8 will be described first.

The salient features of the circuit of Fig. 8 are as follows: The twoinputs are designated a and b and are connected to the control grids of vacuum tubes `70 and 71, respectively. The suppressor grids of tubes 70 and 71 are connected to points 72 and 73 in the screen grid circuits of` tubes 71 and 70, respectively. Point 74 in the common anode circuit of tubes 70 and 71 is connectedto the control grid of tube 75 `and the sum output is taken from a point 76 in its `anode circuit.` Points 72l and 73 are connected `to the grids of tubes 77 and 78 and the carryloutput is connected to point 79 in the common anode circuit of these tubes. The points 76 and 79 are so. selected that they may exhibit either positive or negative potentials relative to ground depending upon the conduction in the tubes 75, 77 and 78.

Consider first the operation of the circuit with positive pulses (binary 1) on both input terminals a and b.l As

-variable adders. third section is alreadypointed out, the circuit under this condition should `With -I- pulses ata and b, the screengrid currents of tubes 70 and 71 are high and the potentials of points 73 and 72 "are relatively low. Since the suppressor grids of these iti tubes are connected to points 73 and72, their pbtential are also lowered. The lowered suppressor Vpotentials decrease the anode currents in the tubes and increasethe' screen grid currents, which `action results in a further' lowering of the suppressor voltages. Finally a condition of stability is reached in which the screen currentis very high andthe anode current is very low or cut ofi entirely. In the presence of a small or zero anode current in both tubes the potential of point 74 is relatively high. This causes high conduction in tube 75 which reduces the potential of point 76 into the negative region. The required negative pulse (binary 0) on line s is therefore produced. Also, since the low potentials of points 72 and 73 on the grids of tubes 77 and 78 reduce their anode currents and raise their anode potentials, the point 79 is lifted into the positive region producing the positive (binary l) carry `on line c as required.

With a positive pulse (1) on one of the terminals a and b and a negative pulse (0) on the other, the Itube having the positive pulse will also have a `relatively high suppressor grid potential due to the high screen grid p otential of the other tube which has a negative pulse on its control grid and therefore low screen current. The resulting high anode current of the tube receiving the positive pulse input lowers the potential of point 74 and the grid of tube 75. The resulting reduction in tube 75 anode current raises the potential of itsanode andA that of point 76 so that a positive pulse (binary 1) on line s is produced as required. Also the conduction in tubes V77 and 78 is suicient to reduce the anode potentialof these tubes enough to produce a negative potential (binary 0) at point 79 and line c, as required. This results from the fact that the grid of the tube 77-78 that is connected to the screen circuit of the tube receiving the negative in"-` put pulse will have its maximum value in the positive direction due to the low screen current, and the grid connected to the screen circuit of the tube receiving the positive input pulse will have a moderately high value in the positive direction `due to partly reduced screen current caused by the high suppressor potential.

With negative potentials (binary 0) at both terminals a and b, negative potentials occur at both lines s and c, as required. The negative potential on line s results from the low anode conduction and high. anode potential of tubes 70 and 71. This results in a relatively high po tential at point 74, high anode current in tube 75, a low tube 75 anode potential and a resulting negative potential at point 76. The negative potential online c results from the high screen potential of tubes 70 and 71. These potentials cause relatively high potentials on the grids of tubes 77 and 78 and the resulting high anode conduction in these tubes causes the potential of point 79 to fall into the negative region.

The 3-variable adder of Fig. 9 has input terminals designateda, b and d, a sum outputdesignated sand a carry output designated c, these markings corresponding to those of basic 3-variable adder 38 in Fig. 1. The response of this adder to the various combinations of positive and negative input pulses is restated as follows:

The tubes 80 and 81 are interconnected in the same manner as tubes 70 and 71 of Fig. 8 and their operation is the.` same. Reviewing this operation, if terminals a and b are both positive the screen grid conduction in the two [tubes is high and points 83 and 84 have negative potentials;l

Since the suppressor grids of these tubes are cross-connected to these points and are therefore negative also, substantially no anode current flows and point 82 has a positive potential resulting from the relatively high anode voltages. If points a and b are both negative, there is little or no conduction in either tube and points 82, S3 and 84 all have positive potentials. -f one of the points a. and b is positive and the other negative the anode conduc-. tion in the tube having the positive potential is high, beingV bolstered by the relatively high potential ot` its suppressor grid which is connected to the screen circ-uit of the other tube, so that its anode potential is relatively low and point' 82 is negative. As for points 83 and 84 under this condition, the potential of the point associated with the conductive tube is negative and that of the point associated with the tube receiving the negative ,input is positive. Points 83 and 84 are connected to the suppressor grids of Atubes 85 and86 the function of which will be explained later. Y v Tubes 87 and 88 are interconnected inthe same manner as tubes 80 and 81 and operate in the same manner. Point 82 is connected to the control grid of tube 87 and its potential serves as the input to this tube. input terminal d is connected to the control grid of .tube 88. The potential at point 89'is applied to the control grid of tube 36.` Point 90, at which a positive or negative potential representing the `sumrdigit is produced, is connected tothe sum output terminal s and also to the control grid of tube 85.

Tubes 85. and 86 generate the *positive or negative potential representing the carry. The anodes of these tubes are'connected in parallel and supplied through a common resistor 91. The arrangement is such that if neither tube is conductive the potential of point 92 is positive (binary 1);, while if either tube is conductive, the fall in anode potential is suflicient to lower point 92 into the negative region (binary O). A negative potential on either vthe control or thesuppressor 'grid will prevent conduction in tubes 85 and 86. Y

Applying the above operating characteristics to a specific situation,` assume that positive pulses are `simultaneously applied to terminals a, b and d. yFor this input, point 82 is positive and points 83 and 84 are negative. Tubes 87 and 8S receive their inputs from points 82 and terminal d and, with these inputs positive, point 90 is positive and point 89 is negative. The positive potential atpoint 90 gives'a positive (binary l) output at point s. The negative potential at point 83 prevents conduction in tube 85 (although 99 is l) andthe negative potential at point 84 (and 89) prevents conduction in tube V86. Therefore point 92 is positive giving a positive potential (binary Vl at carry output terminal c. The other input situationsindicated in the foregoing table may be traced through the circuit of the adder in a similar manner.

We claim: r

' l. Multiplying apparatus in which the multiplier, multiplicand and product are serial binary numbers the digits of which are represented by a succession `of electrical pulses having .a separation interval T with thel pulse rep- 'resenting the least significant digit occurring rst', said pulses being positive when the represented digit is l and negative when the represented digit is 0, said apparatus comprising: a partial product terminal corresponding to each digit of the multiplier; a source of negative pulses having a separation interval T; a multiplicand terminal; a normally unactuated switching means -connected to each partial product terminal and'oper'ativein its unactuated state to connect said partial product terminal to said negative pulse source and operative in its actuated state to connect said partial product terminal to said multiplicand terminal said lastnamed connection containing .means producingy adelay equal to the interval by which the multiplier-digit to which the partial product .terminal corresponds lags therleast signicant digit of kthe multiplier; an electrical actuating means -for each of said y.switching means, each actuating means having rst and second input circuits and operating in response to lcoincident positive pulses applied to its input circuits to actuate and hold actuated its associated switching means; an electrical delay line having as many delay points, including the zero delay point, as there are digits in said multiplier, the delay between successive points being equal tothe interval T; means for'applying the pulses representing the digits of said multiplier to the zero delay point of said line, least significant digit rst; means connecting the first input circuit of the actuating means for the switching means connected to the partial product terminal corresponding to the least significant multiplier digit to the point of maximum delay on said line, and means similarly connectingthe first input circuits of the actuating means for the switching means connected to the partial product terminals corresponding to the remaining multiplier digits of successively higher order to line points of successively lesser delay; means for applying positive pulses to the second input circuits of `said actuating means simultaneously and coincidently with the application of the pulse representing the most significant digit of said multiplier to the zero delay point of said delay line; a normally unactuated multiplicand switchingv means operatingV in its'unactuated state to connect said multiplicand terminal to said source of negative pulses and in its actuated state to apply the pulses representing said `multiplicand to said multiplicand terminal, least significant digit first; means operative subsequently to the said simultaneous application of positive pulses to the second input circuits of said'actuating means to actuate said multiplicand switching means for a period suiicient onlyto encompass the pulses representing said multiplicand, whereby the vpulses representing ,said multiplicand are applied to said multiplicand terminal and thence to said partial product terminals at which they represent the partial products of corresponding order, the

pulses appearing simultaneously on said partial product ,terminals representing the partial product digit columns; and a binary serial column adder having input circuits connected to said partial product terminals anda column sum output terminal at which pulses representing the digits of the product appear.

2. Apparatus as claimed in claim l in which said serial column adder produces carries to higher order columns and in which the number of input circuits of the column adder equals the number of multiplier digits plus the maximum number of carries to a column, means for delaying each carry produced by said column adder by a multiple of T as required to store said carry until the appearance at said partial product terminals of the pulses representing the partial product digit column to which it pertains, and means for applying said delayed .carries to the remaining input circuits of said column adder. l

3. Apparatus as claimed in claim 2 in which there is provided means operative after the `occurrence .of .the pulse'representingthe most 'significant digit of the product at said column sum output terminal for restoring the switching means connected vto said partial product terminals to their unactuated states. I

4. An N-digit-serial column kadder for binarynumbers, wherein VN is aninteger kgreater than 3, `for providing a column sum and appropriate carries to *higher order columns, consisting of a combination of basic Vtwo-variable and 'three-variable binary adders leach producing from two and threedigit binary inputs, respectively, a sum and a carry each of which is one of the two `binary digits l and O, said combination comprising: ym cascaded adder sections, m being not less `than 2, each, except the last section in the cascade, consisting of a plurality of said basic adders cascaded Yby connecting the sum output of each to an input of the next succeeding basic adder in the cascade, the last section consisting of a single 'basic adder; means for cascading said sections by connecting fthe carry outputs produced Aby the -cascaded adders thereinuto the unused inputs of .the next succeeding section in the section cascade, the unused inputs in the first section of said cascade being equal to N and the unused inputs in each succeeding section in said cascade being equal to the number of carry outputs of the preceding section, the sum produced by the cascaded adders of the first section constituting the column sum and the sums produced by the remaining sections and the carry produced by the last section in the section cascade constituting the carries to higher order columns; means for delaying each carry to a higher order column by an interval equal to the period between said serial columns multiplied by the number of the higher order column, with respect to the column being added, to which the carry belongs; and means for applying each of said delayed carries to one of the unused inputs of said rst section; the first section, when N is even, consisting of one two-variable adder and three-variable adders and, when N is odd, consisting of three-variable adders and, when cis odd, consisting of three-variable adders, c being the number of carry outputs of the preceding adder section in the section cascade.

5. An N-digit parallel column adder for binary numbers, wherein N is an integer greater than 3, for providing a column sum and appropriate carries to higher order columns consisting of a combination of basic binary adders of the two-variable and three-variable type each producing from two and three digit binary inputs, respective ly, a sum and a carry each of which is one of the two binary digits l and 0, said combination comprising: m cascaded adder sections, m being not less than 2, each, except the last section in the cascade, consisting of a plurality of said basic adders cascaded by connecting the adders of the first section constituting the column sum and the sums produced by the remaining sections and the carry produced by the last section in the section cascade constituting the carries to higher order columns; the first section, when N is even, consisting of one twovariable adder and three-variable adders and, when N is odd, consisting of three-variable adders; each remaining section consisting, when cis even, of one two-variable adder and three-variable adders and, when cis odd, consisting of l adders each having three inputs, a sum output and a carry sum output of each to an input of the next succeeding basic adder inthe cascade, the last section in the section cascade consisting of a single basic adder; means for cascading said sections by connecting the carry outputs produced by the cascaded adders therein to the unused inputs of the next succeeding section in the section cascade, the unused inputs in the first section of said cascade being equal to N and the unused inputs in each succeeding section in said cascade being equal tothe number of carry outputs of the preceding section, the sum produced by the cascaded output, and a fourth basic adder having two inputs, a sum output and a carry output; means connecting the sum output of said rst basic adder to one of the inputs of said second basic adder; means connecting the sum output of said second basic adder to one of the inputs of said fourth basic adder; means connecting the carry outputs of said first, second and fourth basic adders to the three inputs of said third basic adder; means delaying the sum output of said third basic adder by the said column separation interval and applying said delayed sum output to an unused input in the group of inputs provided by said first, second and fourth adders; means delaying the carry output of said third adder by twice said interval and applying said delayed carry to an unused input of said group of inputs; and means for applying the column digits to the remaining unused inputs of said group, the column sum appearing at the sum output of said fourth basic adder.

References (Zited in the le of this patent UNlTED STATES PATENTS 2,638,267 Hartley et al May l2, 1953 2,861,741 Bire Nov. 25, 1958 2,888,202 Blankenbaker et al May 26, 1959 

